A semiconductor apparatus, one or more of which are included in an integrated circuit (IC), includes a number of electronic devices. One way in which to represent a semiconductor device is with a plan view diagram referred to as a layout diagram (hereinafter, layout). A layout is hierarchical and is decomposed into modules which carry out higher-level functions as required by the semiconductor device's design specifications. In some circumstances, a semi-custom design (SCD) project decomposes the modules into macro cells, standard cells and custom cells.
For a given SCD project, a custom cell is designed with an arrangement that is specific to the given SCD project in order to provide (in operation) a higher-level logic function that is specific to the SCD project. By contrast, a library of standard cells is designed with no particular project in mind and includes standard cells which provide (in operation) common, lower-level logic functions. Designing a layout using a library of standard cells (standard cell library) which includes physical cell structures having a predetermined uniform layout pitch facilitates dense packing of the cells, and, thus, dense placement of the transistors.
A standard cell includes a device layer and a first array on the device layer. The standard device layer includes one or more semiconductor devices, and inter-layer connection structures correspondingly connected to one or more components of the corresponding one or more semiconductor devices. A standard first array includes a stacked arrangement of vias interspersed with corresponding first segments of corresponding M(i)˜M(N) metallization layers (where i and N are non-negative integers and i<N) such that the first segments of the M(N) metallization layer are connected to corresponding one or more semiconductor devices (in the device layer) underlying the M(i) layer. Second segments of the M(N) metallization layer connect corresponding first segments of the M(N) metallization layer in the first standard arrays and thereby connect the corresponding standard cells. Adopting a minimal number of configurations for the first arrays further facilitates dense packing of cells.